1. Field of the Invention
The present invention relates to a fast logic circuit formed using selector circuits, as well as a method for forming such the logic circuit.
2. Description of Related Art
There have been published many researches with respect to fast logic circuits so far. Many of those fast logic circuits use pass transistors.
For example, Proceeding of IEEE 1994 Custom Integrated Circuits Conference (pp.603-606) (hereafter, to be referred as document 1) has proposed a method for forming a logic circuit by combining 2-input 1-output pass transistor selectors composed of only n-channel field-effect transistors and delay time improvement buffer inverters respectively. In this case, an object fast logic circuit is successfully formed as a compact circuit provided with less transistors through the use of the characteristics of the pass transistor that can realize a complicated logic function with less transistors.
On the other hand, IEEE Journal of Solid-State Circuits (Vol.25, No.2, pp.388-395) (hereafter, to be referred to as document 2) has proposed a differential fast pass transistor logic circuit, which is referred to as a CPL (Complementary Pass transistor Logic). Just like in the document 1, the CPL logic circuit is composed of 2-input 1-output pass transistor selectors composed of only n-channel field-effect transistors and buffer inverters respectively. The most typical characteristic of the CPL is that two 2-input 1-output pass transistor selectors are always paired so as to be formed as a differential logic circuit that uses signals of both positive and negative polarities. This is different from the technology disclosed in the document 1. Such way, the CPL forms a fast logic circuit by taking advantage of the characteristics of both pass transistor circuit that can realize a complicated logic function with less transistors and differential circuit that requires no inverter for polarity matching. According to the document 2, the CPL has actually realized a full adder 2.5 times faster than a CMOS circuit.
In addition, IEEE International Solid-state Circuits Conference Digest of Technical Papers (pp.90-91, 1993) (hereafter, to be referred to as document 3) has proposed a pass transistor logic circuit referred to as a DPL (Double Pass transistor Logic). Similarly to the CPL, the DPL logic circuit is composed of differential pass transistor selectors so as to use signals of both positive and negative polarities. Unlike the CPL, however, each pass transistor selector is composed of both n-channel and p-channel field-effect transistors. In the case of the pass transistors proposed in the documents 1 and 2, each selector circuit is composed of only n-channel field-effect transistors. Thus, a voltage drop equivalent to the threshold voltage of such a transistor appears at the output of the selector circuit. Consequently, if the supply voltage is low, the circuit cannot operate fast. In the case of the DPL, each selector uses p-channel field-effect transistors together with n-channel field-effect transistors thereby avoiding such a problem of voltage drop equivalent to the threshold voltage value. Consequently, the circuit can operate fast even at a low supply voltage.
Furthermore, U.S. Pat. No. 5,040,139 (hereafter, to be referred to as document 4), U.S. Pat. No. 5,162,666 (hereafter, to be referred to as document 5), and U.S. Pat. No. 5,200,907 (hereafter, to be referred to as document 6) have disclosed methods for forming logic circuits using selectors composed mainly of pass transistor circuits referred to as a TGM circuit (Transmission Gate Multiplexer) respectively. A TGM composed mainly of pass transistor circuits can operate faster than XOR, NAND, and NOR gates composed of a CMOS circuit respectively, so a TGM based logic circuit can operate faster than any of conventional CMOS based logic circuits.
Generally, an actual large logic circuit has a plurality of paths between an input and an output respectively. Consequently, a time required until an output signal is determined (that is, a delay time of the output signal) is decided by the delay time of a (so-called critical) path among the paths, which has the largest total delay time of its elements of a transistor circuit such as a transistor, etc. In addition, if there are a plurality of output signals, the operation speed of a logic circuit is decided by the delay time of the output signal whose delay time is the largest.
Consequently, if there is even one path whose delay time is extremely large, the circuit, as a whole, cannot operate fast even when the delay times of all other paths are very small and they can operate fast. In order to form a large and fast logic circuit actually, therefore, it is very important to make the number of steps in all the paths equal by all means and avoid forming a path having an extremely large delay time when in designing the logic circuit.
In spite of such the circumstances, none of the documents described for the conventional technologies have guaranteed any method for preventing such an extremely slow path from being formed as described above, although those conventional technologies are very effective for improving the operation speed of a circuit itself. Furthermore, none of the documents 1 to 6 mentions any method for forming a logic circuit so as to make the number of steps in all its paths as equal as possible.
And, all the input signals do not arrive necessarily at the same time in an actual circuit; there is always a specific signal, which is often delayed from others. The delay time of the entire logic circuit in such a case becomes the sum of the delay time of the circuit itself and the delay time of the input signal, which is delayed from others. In other words, even when the delay time of an object path is small, if there is any signal which arrives extremely late in the path, then the operation speed of the entire circuit is decided by the operation speed of the path. Consequently, if there is any input signal that is delayed extremely, the logic circuit should be formed so that the number of steps in the path related to the input signal is reduced by all means and the delay times of all the paths in the circuit become equal.
Under such the circumstances, it is an object of the present invention to provide a fast logic circuit by arranging the number of steps so as to be equal in all the paths of the logical circuit and avoiding existence of a critical path whose delay time is extremely large.
It is another object of the present invention to provide a fast logic circuit formed so that if a specific input signal is far delayed from others, the delay time is taken into account thereby to arrange the number of steps is reduced by all means in the path related to the delayed signal when in forming the object logical circuit.
It is further another object of the present invention to provide a method for forming a logic circuit that can avoid having a critical path whose delay time is extremely large.
It is further another object of the present invention to provide a method for forming a logic circuit that can avoid having a critical path whose delay time is extremely large by considering an increase of the delay time of a specific input signal, which is expected to be delayed extremely from others.
In order to achieve the above objects, a preferred form of the present invention is a logic circuit (C1 shown in FIG. 1) including: the first selector (S1) in which the control input S is controlled by the first input signal (IN1), and the input signal I1 or I0 is controlled by the second input signal (IN2), and the output O is connected to the first node (N1); and the third selector (S3) in which the control input S is controlled by the first node (N1), the input I1 is controlled by the third input signal (IN3), the input I0 is controlled by the first input signal (IN1), and the output O is connected to the first output signal (OUT1).
Another preferred form of the present invention is a logic circuit (C41 shown in FIG. 2) including: the 41st selector (S41) in which the control input S is controlled by the first input signal (IN1), the input signal I1 is controlled by the third input signal (IN3), and the output O is connected to the 41st node (N41); and the 43rd selector (S43) in which the control input S is controlled by the second input signal (IN2), one of the input I1 and I0 is controlled by the 41st node (N41), the other is controlled by the first input signal (IN1), and the output O is connected to the first output signal (OUT1).
Further another preferred form of the present invention is a logical circuit (C1 shown in FIG. 1) including: the first selector (S1) in which the control input S is controlled by the first input signal (IN1), the input I1 is controlled by the second input signal (IN2), the input I0 is connected to a constant potential (GND), and the output O is connected to the first node (N1); the second selector (S2) in which the control input S is controlled by the first input signal (IN1), the input I1 is controlled by the fourth input signal (IN4), the input I0 is controlled by the fifth input signal (IN5), and the output O is connected to the second node (N2); and the third selector (S3) in which the control input S is controlled by the first node (N1), the input I1 is controlled by the third input signal (IN3), the input I0 is controlled by the second node (N2), and the output O is connected to the first output signal (OUT1).
Further another preferred form of the present invention is a logic circuit (C21 shown in FIG. 1) including: the 21st selector (S21) in which the control input S is controlled by the first input signal (IN1), the input signal I1 is connected to a constant potential (GND), and the input signal I0 is controlled by the second input signal (IN2), and the output O is connected to the 21st node (N21); the 22nd selector (S22) in which the control input S is controlled by the first input signal (IN1), the input I1 is controlled by the fifth input signal (IN5), the input signal I0 is controlled by the fourth input signal (IN4), and the output O is connected to the 22nd node (N22); and the 23rd selector (S23) in which the control input S is controlled by the 21st node (N21), the input I1 is controlled by the third input signal (IN3), the input I0 is controlled by the 22nd node (N22), and the output is connected to the first output (OUT1).
Further another preferred form of the present invention is a logical circuit (C41 shown in FIG. 2) including: the 41st selector (S41) in which the control input S is controlled by the first input signal (IN1), the input I1 is controlled by the third input signal (IN3), the input I0 is controlled by the fifth input signal (IN5), and the output O is connected to the 41st node (N41); the 42nd selector (S42) in which the control input S is controlled by the first input signal (IN1), the input I1 is controlled by the fourth input signal (IN4), the input I0 is controlled by the fifth input signal (IN5), and the output O is connected to the 42nd node (N42); and the 43rd selector (S43) in which the control input S is controlled by the second input signal (IN2), the input I1 is controlled by the 41st node (N41), the input I0 is controlled by the 42nd node (N42), and the output O is connected to the first output signal (OUT1).
Further another preferred form of the present invention is a logical circuit (C51 shown in FIG. 2) including: the 51st selector (S51) in which the control input S is controlled by the first input signal (IN1), the input I1 is controlled by the fifth input signal (IN5), the input I0 is controlled by the third input signal (IN3), and the output O is connected to the 51st node (N51); the 52nd selector (S52) in which the control input S is controlled by the first input signal (IN1), the input I1 is controlled by the fifth input signal (IN5), the input I0 is controlled by the fourth input signal (IN4), and the output O is connected to the 52nd node (N52); and the 53rd selector (S53) in which the control input S is controlled by the second input signal (IN2), the input I1 is controlled by the 51st node (N51), the input I0 is controlled by the 52nd node (N52), and the output O is connected to the first output signal (OUT1).
Further another preferred form of the present invention is a logical circuit (C61 shown in FIG. 2) including: the 61st selector (S61) in which the control input S is controlled by the second input signal (IN2), the input I1 is controlled by the fourth input signal (IN4), the input I0 is controlled by the fifth input signal (IN5), and the output O is connected to the 61st node (N61); the 62nd selector (S62) in which the control input S is controlled by the third input signal (IN3), the input I1 is controlled by the fourth input signal (IN4), the input I0 is controlled by the fifth input signal (IN5), and the output O is connected to the 62nd node (N62); and the 63rd selector (S63) in which the control input S is controlled by the first input signal (IN1), the input I1 is controlled by the 61st node (N61), the input I0 is controlled by the 62nd node (N62), and the output O is connected to the first output signal (OUT1).
Further another preferred form of the present invention is a logical circuit (C71 shown in FIG. 2) including: the 71st selector (S71) in which the control input S is controlled by the third input signal (IN3), the input I1 is controlled by the fourth input signal (IN4), the input I0 is controlled by the fifth input signal (IN5), and the output O is connected to the 71st node (N71); the 72nd selector (S72) in which the control input S is controlled by the first input signal (IN1), the input I1 is controlled by the fourth input signal (IN4), the input I0 is controlled by the 71st node (N71), and the output O is connected to the 72nd node (N72); the 73rd selector (S73) in which the control input S is controlled by the first input signal (IN1), the input I1 is controlled by the fifth input signal (IN5), the input I0 is controlled by the 71st node (N71), and the output O is connected to the 73rd node (N73); and the 74th selector (S74) in which the control input S is controlled by the second input signal (IN2), the input I1 is controlled by the 72nd node (N72), the input I0 is controlled by the 73rd node (N73), and the output O is connected to the first output signal (OUT1).
Further another preferred form of the present invention is a logical circuit (C81 shown in FIG. 2) including: the 81st selector (S81) in which the control input S is controlled by the second input signal (IN2), the input I1 is controlled by the fourth input signal (IN4), the input I0 is controlled by the fifth input signal (IN5), and the output O is connected to the 81st node (N81); the 82nd selector (S82) in which the control input S is controlled by the first input signal (IN1), the input I1 is controlled by the 81st node (N81), the input I0 is controlled by the fourth input signal (IN4), and the output O is connected to the 82nd node (N82); the 83rd selector (S83) in which the control input S is controlled by the first input signal (IN1), the input I1 is controlled by the 81st node (N81), the input I0 is controlled by the fifth input signal (IN5), and the output O is connected to the 83rd node (N83); and the 84th selector (S84), in which the control input S is controlled by the third input signal (IN3), the input I1 is controlled by the 82nd node (N82), the input I0 is controlled by the 83rd node (N83), and the output O is connected to the first output signal (OUT1).
Further another preferred embodiment of the present invention is logic circuits C1, C11, C21, and C31 shown in FIG. 1 and logic circuits C41, C51, C61, C71, and C81 shown in FIG. 2 including respectively a selector (C100 shown in the a-row in FIG. 3), which includes: the 100th n-channel field-effect transistor (TN100) in which the gate is controlled by the 104th node (N104) and a source drain path is connected between the input I0 and the 100th node (N100); the 101st n-channel field-effect transistor (TN101) in which the gate is controlled by the control input S and a source drain path is connected between the input I1 and the 100th node (N100); the 104th p-channel field-effect transistor (TN104) in which the gate is controlled by the control input S and a source drain path is connected between the first operation potential point (VDD) and the 104th node (N104); the 105th n-channel field-effect transistor (TN105) in which the gate is controlled by the control input S and a source drain path is connected between the second operation potential point (GND) and the 104th node (N104); the 102nd p-channel field-effect transistor (TP102) in which the gate is controlled by the 100th node (N100) and a source drain path is connected between the first operation potential point (VDD) and an output; the 103rd n-channel field-effect transistor (TN103) in which the gate is controlled by the 100th node (N100) and a source drain path is connected between the second operation potential point (GND) and an output.
Further another preferred embodiment of the present invention is logic circuits C1, C11, C21, and C31 shown in FIG. 1 and logic circuits C41, C51, C61, C71, and C81 shown in FIG. 2 including respectively a selector (C200 shown in the a-row in FIG. 3), which includes: the 200th n-channel field-effect transistor (TN200) in which the gate is controlled by a complementary signal (Sxe2x80x2) of the control input S and a source drain path is connected between the input I0 and the 200th node (N200); the 201st n-channel field-effect transistor (TN201) in which the gate is controlled by the control input S and a source drain path is connected between the input I1 and the 200th node (N200); the 202nd n-channel field-effect transistor (TN202) in which the gate is controlled by a complementary signal (Sxe2x80x2) of the control input S and a source drain path is connected between the complementary signal (I0xe2x80x2) of the input I0 and the 202nd node (N202); the 203rd n-channel field-effect transistor (TN203) in which the gate is controlled by the control input S and a source drain path is connected between the complementary signal (I1xe2x80x2) and the 202nd node (N202); the 206th p-channel field-effect transistor (TP206) in which the gate is controlled by the 200th node (N200) and a source drain path is connected between the first operation potential point (VDD) and a complementary signal (OUTxe2x80x2) of an output; the 207th n-channel field-effect transistor (TN207) in which the gate controlled by the 200th node (N200) and a source drain path is connected between the second operation potential point (GND) and a complementary signal (OUTxe2x80x2) of an output; the 208th p-channel field-effect transistor (TP208) in which the gate controlled by the 202nd node (N202) and a source drain path is connected between the first operation potential point (VDD) and an output; the 209th n-channel field-effect transistor (TN209) in which the gate is controlled by the 202th node (N202) and a source drain path is connected between the second operation potential point (GND) and an output.
Further another preferred embodiment of the present invention is a logic circuit (C120 shown in FIG. 4), which includes: the 127th p-channel field-effect transistor (TP127) in which the gate is controlled by the first input signal (IN1) and a source drain path is connected between the first operation potential point (VDD) and the 127th node (N127); the 127th n-channel field-effect transistor (TN127) in which the gate is controlled by the first input signal (IN1) and a source drain path is connected between the second operation potential point (GND) and the 127th node (N127);
the 128th n-channel field-effect transistor (TN128) in which the gate is controlled by the 127th node (N127) and a source drain path is connected to the 126th node (N128); the 129th n-channel field-effect transistor (TN129) in which the gate is controlled by the first input signal (IN1) and a source drain path is connected between the second input signal (IN2) and the 128th node (N128);
the 121st p-channel field-effect transistor (TP121) in which the gate is controlled by the 128th node (N128) and a source drain path is connected between the first operation potential point (VDD) and the 121st node (N121); the 121st n-channel field-effect transistor (TN121) in which the gate is controlled by the 121st node (N121) and a source drain path is connected between the second operation potential point (GND) and the 121th node (N121);
the 125th p-channel field-effect transistor (TP125) in which the gate is controlled by the 121st node (N121) and a source drain path is connected between the third input signal (IN3) and the 125th node (N125); the 126th n-channel field-effect transistor (TN126) in which the gate is controlled by the 128th node (N128) and a source drain path is connected between the 124th code (N124) controlled by the first input signal (IN1), and the 125the node (N125).
Further another preferred embodiment of the present invention is a logic circuit (C120 shown in the a-row in FIG. 4), which includes: the 120th p-channel field-effect transistor (TP120) in which the gate is controlled by the first input signal (IN1) and a source drain path is connected between the first operation potential point (VDD) and the 120th node (N120);
the 120th n-channel field-effect transistor (TN120) in which the gate is controlled by the first input signal (IN1) and a source drain path is connected between the second operation potential point (GND) and the 120th node (N120);
the 123rd n-channel field-effect transistor (TN123) in which the gate is controlled by the 120th node (N120) and a source drain path is connected between the fifth input signal (IN5) and the 124th node (N124); the 124th n-channel field-effect transistor (TN124) in which the gate is controlled by the first input signal (IN1) and a source drain path is connected between the fourth input signal (IN4) and the 124th node (N124);
the 121st p-channel field-effect transistor (TP121) in which the gate is controlled by the 130th node (N130) and a source drain path is connected between the first operation potential point (VDD) and the 121st node (N121); the 121st n-channel field-effect transistor (TN121) in which the gate is controlled by the 130th node (N130) and a source drain path is connected between the second operation potential point (GND) and the 121st node (N121);
the 125th n-channel field-effect transistor (TN125) in which the gate is controlled by the 121st node (N121) and a source drain path is connected between the third input signal (IN3) and the 125th node (N125); the 126th n-channel field-effect transistor (TN126) in which the gate is controlled by the 130th node (N130) and a source drain path is connected between the 124th node (N124)and the 125th node (N125);
the 127th p-channel field-effect transistor (TP127) in which the gate is controlled by the first input signal (IN1) and a source drain path is connected between the first operation potential point (VDD) and the 127th node (N127); the 127th n-channel field-effect transistor (TN127) in which the gate is controlled by the first input signal (IN1) and a source drain path is connected between the second operation potential point (GND) and the 127th node (N127);
the 128th n-channel field-effect transistor (TN128) in which the gate is controlled by the 127th node (N127) and a source drain path is connected between the first (VDD) or second operation point (GND) and the 128th node (N128); the 129th n-channel field-effect transistor (TN129) in which the gate is controlled by the first input signal (IN1) and a source drain path is connected between the second input signal (IN2) and the 128th node (N128);
the 130th p-channel field-effect transistor (TP130) in which the gate is controlled by the 128th node (N128) and a source drain path is connected between the first operation potential point (VDD) and the 130th node (N130); the 130th n-channel field-effect transistor (TN130) in which the gate is controlled by the 128th node (N128) and a source drain path is connected between the second operation potential point (GND) and the 130th node (N130);
the 122nd p-channel field-effect transistor (TP122) in which the gate is controlled by the 125th node (N125) and a source drain path is connected between the first operation potential point (VDD) and the first output signal (OUT1); the 122nd n-channel field-effect transistor (TN122) in which the gate is controlled by the 125th node (N125) and a source drain path is connected between the second operation potential point (GND) and the first output signal (OUT1).
Further another preferred embodiment of the present invention is a logic circuit (C140 shown in the a-row in FIG. 5), which includes: the 140th p-channel field-effect transistor (TP140) in which the gate is controlled by the first input signal (IN1) and a source drain path is connected between the first operation potential point (VDD) and the 140th node (N140); the 140th n-channel field-effect transistor (TN140) in which the gate is controlled by the first input signal (IN1) and a source drain path is connected between the second operation potential point (GND) and the 140th node (N140);
the 143rd n-channel field-effect transistor (TN143) in which the gate is controlled by the 140th node (N140) and a source drain path is connected between the fourth input signal (IN4) and the 144th node (N144); the 144th n-channel field-effect transistor (TN144) in which the gate is controlled by the first input signal (IN1) and a source drain path is connected between the fifth input signal (IN5) and the 144th node (N144);
the 141st p-channel field-effect transistor (TP141) in which the gate is controlled by the 150th node (N150) and a source drain path is connected between the first operation potential point (VDD) and the 141st node (N141); the 141st n-channel field-effect transistor (TN141) in which the gate is controlled by the 150th node (N150) and a source drain path is connected between the second operation potential point (GND)and the 141st node (N141);
the 145th n-channel field-effect transistor (TN145) in which the gate is controlled by the 141st node (N141) and a source drain path is connected between the third input signal (IN3) and the 145th node (N145); the 146th n-channel field-effect transistor (TN146) in which the gate is controlled by the 150th node (N150) and a source drain path is connected between the 144th node (N144) and the 145th node (N145);
the 147th p-channel field-effect transistor (TP147) in which the gate is controlled by the first input signal (IN1) and a source drain path is connected between the first operation potential point (VDD) and the 147th node (N147); the 147th n-channel field-effect transistor (TN147) in which the gate is controlled by the first input signal (IN1) and a source drain path is connected between the second operation potential point (GND) and the 147th node (N147);
the 148th n-channel field-effect transistor (TN148) in which the gate is controlled by the 147th node (N147) and a source drain path is connected between the second input signal (IN2) and the 148th node (N148); the 149th n-channel field-effect transistor (TN149) in which the gate is controlled by the first input signal (IN1) and a source drain path is connected between the first operation potential point (VDD) or the second operation potential point (GND) and the 148th node (N148);
the 150th p-channel field-effect transistor (TP150) in which the gate is controlled by the 148th node (N148) and a source drain path is connected between the first operation potential point (VDD) and the 150th node (N150); the 150th n-channel field-effect transistor (TN150) in which the gate is controlled by the 148th node (N148) and a source drain path is connected between the second operation potential point (GND) and the 150th node (N150);
the 142nd p-channel field-effect transistor (TP142) in which the gate is controlled by the 145th node (N145) and a source drain path is connected between the first operation potential point (VDD) and the first output signal (OUT1); the 142nd n-channel field-effect transistor (TN142) in which the gate is controlled by the 145th node (N145) and a source drain path is connected between the second operation potential point (GND) and the first output signal (OUT1).
Further another preferred embodiment of the present invention is a logic circuit (C160 shown in the a-row in FIG. 11), which includes: the 160th p-channel field-effect transistor (TP160) in which the gate is controlled by the first input signal (IN1) and a source drain path is connected between the first operation potential point (VDD) and the 160th node (N160); the 160th n-channel field-effect transistor (TN160) in which the gate is controlled by the first input signal (IN1) and a source drain path is connected between the second operation potential point (GND) and the 160th node (N160);
the 163rd n-channel field-effect transistor (TN163) in which the gate is controlled by the 160th node (N160) and a source drain path is connected between the fifth input signal (IN5) and the 163rd node (N163); the 164th n-channel field-effect transistor (TN164) in which the gate is controlled by the first input signal (IN1) and a source drain path is connected between the fourth input signal (IN4)and the 163rd node (N163);
the 161st p-channel field-effect transistor (TP161) in which the gate is controlled by the 168th node (N168) and a source drain path is connected between the first operation potential point (VDD) and the 161st node (N161); the 161st n-channel field-effect transistor (TN161) in which the gate is controlled by the 168th node (N168) and a source drain path is connected between the second operation potential point (GND) and the 161st node (N161);
the 165th n-channel field-effect transistor (TN165) in which the gate is controlled by the 161st node (N161) and a source drain path is connected between the third input signal (IN3) and the 165th node (N165); the 166th n-channel field-effect transistor (TN166) in which the gate is controlled by the 168th node (N168) and a source drain path is connected between the 163rd node (N163) and the 165th node (N165);
the 167th p-channel field-effect transistor (TP167) in which the gate is controlled by the first input signal (IN1) and a source drain path is connected between the first operation potential point (VDD) and the 168th node (N168); the 168th p-channel field-effect transistor (TP168) in which the gate is controlled by the second input signal (IN2) and a source drain path is connected between the first operation potential point (VDD) and the 168th node (N168); the 167th n-channel field-effect transistor (TN167) in which the gate is controlled by the second input signal (IN2) and a source drain path is connected between the 168th node (N168) and the 167th node (N167); the 167th n-channel field-effect transistor (TN167) in which the gate is controlled by the first input signal (IN1) and a source drain path is connected between the second operation potential point (GND) and the 167th node (N167);
the 162nd p-channel field-effect transistor (TP162) in which the gate is controlled by the 165th node (N165) and a source drain path is connected between the first operation potential point (VDD) and the first output signal (OUT1); and the 162nd n-channel field-effect transistor (TN162) in which the gate is controlled by the 165th node (N165) and a source drain path is connected between the second operation potential point (GND) and the first output signal (OUT1).
Further another preferred embodiment of the present invention is a logic circuit (C180 shown in the a-row in FIG. 12), which includes: the 184th p-channel field-effect transistor (TP184) in which the gate is controlled by the first input signal (IN1) and a source drain path is connected between the first operation potential point (VDD) and the 185th node (N185); the 185th p-channel field-effect transistor (TP185) in which the gate is controlled by the second input signal (IN2) and a source drain path is connected between the first operation potential point (VDD) and the 185th node (N185); the 184th n-channel field-effect transistor (TN184) in which the gate is controlled by the second input signal (IN2) and a source drain path is connected between the 185th node (N185) and the 184th node (N184); the 185th n-channel field-effect transistor (TN185) in which the gate is controlled by the first input signal (IN1) and a source drain path is connected between the second operation potential point (GND) and the 184th node (N184);
the 180th p-channel field-effect transistor (TP180) in which the gate is controlled by the 185th node (N185) and a source drain path is connected between the first operation potential point (VDD) and the 180th node (N180); the 180th n-channel field-effect transistor (TN180) in which the gate is controlled by the 185th node (N185) and a source drain path is connected between the second operation potential point (GND) and the 180th node (N180);
the 182nd n-channel field-effect transistor (TN182) in which the gate is controlled by the 180th node (N180) and a source drain path is connected between the third input signal (IN3) and the 182nd node (N182); the 183rd n-channel field-effect transistor (TN183) in which the gate is controlled by the 185th node (N185) and a source drain path is connected between the first input signal (IN1) and the 182nd node (N182); the 181st p-channel field-effect transistor (TP181) in which the gate is controlled by the 182nd node (N182) and a source drain path is connected between the first operation potential point (VDD) and the first output signal (OUT1); the 181st n-channel field-effect transistor (TN181) in which the gate is controlled by the 182nd node (N182) and a source drain path is connected between the second operation potential point (GND) and the first output signal (OUT1).